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OCTAL D FLIP-FLOP WITH CLEAR
The SN54 / 74LS273 is a high-speed 8-Bit Register. The register consists of eight D-Type Flip-Flops with a Common Clock and an asynchronous active LOW Master Reset. This device is supplied in a 20-pin package featuring 0.3 inch lead spacing.
SN54/74LS273
* * * *
8-Bit High Speed Register Parallel Register Common Clock and Master Reset Input Clamp Diodes Limit High-Speed Termination Effects CONNECTION DIAGRAM DIP (TOP VIEW)
VCC 20 Q7 19 D7 18 D6 17 Q6 16 Q5 15 D5 14 D4 13 Q4 12 CP 11
OCTAL D FLIP-FLOP WITH CLEAR
LOW POWER SCHOTTKY
20 1
J SUFFIX CERAMIC CASE 732-03
1 MR
2 Q0
3 D0
4 D1
5 Q1
6 Q2
7 D2
8 D3
9 Q3
10 GND
20 1
N SUFFIX PLASTIC CASE 738-03
PIN NAMES
LOADING (Note a) HIGH LOW 0.25 U.L. 0.25 U.L. 0.25 U.L. 5 (2.5) U.L.
CP D0 - D7 MR Q0 - Q7
Clock (Active HIGH Going Edge) Input Data Inputs Master Reset (Active LOW) Input Register Outputs (Note b)
0.5 U.L. 0.5 U.L. 0.5 U.L. 10 U.L.
20 1
DW SUFFIX SOIC CASE 751D-03
NOTES: a) 1 TTL Unit Load (U.L.) = 40 A HIGH/1.6 mA LOW. b) The Output LOW drive factor is 2.5 U.L. for Military (54) and 5 U.L. for Commercial (74) Temperature Ranges.
ORDERING INFORMATION
SN54LSXXXJ Ceramic SN74LSXXXN Plastic SN74LSXXXDW SOIC
TRUTH TABLE
MR L H H CP X Dx X H L Qx L H L
H = HIGH Logic Level L = LOW Logic Level X = Immaterial
LOGIC DIAGRAM
11
3
4
7
8
13
14
17
18
D0
D1
D2
D3
D4
D5
D6
D7
CP CP D CD Q CP D CD Q CP D CD Q CP D CD Q CP D CD Q CP D CD Q CP D CD Q CP D CD Q
1
MR
VCC = PIN 20 GND = PIN 10 = PIN NUMBERS
Q0
2
Q1
5
Q2
6
Q3
9
Q4
12
Q5
15
Q6
16
Q7
19
FAST AND LS TTL DATA 5-447
SN54/74LS273
FUNCTIONAL DESCRIPTION The SN54 / 74LS273 is an 8-Bit Parallel Register with a common Clock and common Master Reset. When the MR input is LOW, the Q outputs are LOW, independent of the other inputs. Information meeting the setup and hold time requirements of the D inputs is transferred to the Q outputs on the LOW-to-HIGH transition of the clock input.
GUARANTEED OPERATING RANGES
Symbol VCC TA IOH IOL Supply Voltage Operating Ambient Temperature Range Output Current -- High Output Current -- Low Parameter 54 74 54 74 54, 74 54 74 Min 4.5 4.75 - 55 0 Typ 5.0 5.0 25 25 Max 5.5 5.25 125 70 - 0.4 4.0 8.0 Unit V C mA mA
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
Limits Symbol VIH VIL VIK VOH Parameter Input HIGH Voltage 54 Input LOW Voltage 74 Input Clamp Diode Voltage 54 Output HIGH Voltage 74 54, 74 VOL Output LOW Voltage 74 Input HIGH Current 0.1 Input LOW Current Short Circuit Current (Note 1) Power Supply Current - 20 - 0.4 - 100 27 0.35 0.5 20 IIH IIL IOS ICC V A mA mA mA mA 2.7 3.5 0.25 0.4 V V 2.5 - 0.65 3.5 0.8 - 1.5 V V Min 2.0 0.7 V Typ Max Unit V Test Conditions Guaranteed Input HIGH Voltage for All Inputs Guaranteed Input LOW Voltage for All Inputs VCC = MIN, IIN = - 18 mA VCC = MIN, IOH = MAX, VIN = VIH or VIL per Truth Table IOL = 4.0 mA IOL = 8.0 mA VCC = VCC MIN, VIN = VIL or VIH per Truth Table
VCC = MAX, VIN = 2.7 V VCC = MAX, VIN = 7.0 V VCC = MAX, VIN = 0.4 V VCC = MAX VCC = MAX
Note 1: Not more than one output should be shorted at a time, nor for more than 1 second.
AC CHARACTERISTICS (TA = 25C, VCC = 5.0 V)
Limits Symbol fMAX tPHL tPLH tPHL Parameter Maximum Input Clock Frequency Propagation Delay, MR to Q Output Propagation Delay, Clock to Output Min 30 Typ 40 18 17 18 27 27 27 Max Unit MHz ns ns Test Conditions Figure 1 Figure 2 Figure 1
FAST AND LS TTL DATA 5-448
SN54/74LS273
AC SETUP REQUIREMENTS (TA = 25C, VCC = 5.0 V)
Limits Symbol tw ts th trec Parameter Pulse Width, Clock or Clear Data Setup Time Hold Time Recovery Time Min 20 20 5.0 25 Typ Max Unit ns ns ns ns Test Conditions Figure 1 Figure 1 Figure 1 Figure 2
AC WAVEFORMS
1/f max tW CP 1.3 V ts(H) 1.3 V 1.3 V ts(L) 1.3 V MR 1.3 V trec CP tPHL Qn tPLH Qn 1.3 V 1.3 V 1.3 V 1.3 V 1.3 V
tW
th(H) 1.3 V tPLH 1.3 V
th(L) 1.3 V 1.3 V
D
*
tPHL 1.3 V
Qn
tPHL
tPLH
*The shaded areas indicate when the input is permitted to *change for predictable output performance.
Figure 1. Clock to Output Delays, Clock Pulse Width, Frequency, Setup and Hold Times Data to Clock
Figure 2. Master Reset to Output Delay, Master Reset Pulse Width, and Master Reset Recovery Time
DEFINITION OF TERMS SETUP TIME (ts) -- is defined as the minimum time required for the correct logic level to be present at the logic input prior to the clock transition from LOW-to-HIGH in order to be recognized and transferred to the outputs. HOLD TIME (th) -- is defined as the minimum time following the clock transition from LOW-to-HIGH that the logic level must be maintained at the input in order to ensure continued recognition. A negative HOLD TIME indicates that the correct logic level may be released prior to the clock transition from LOW-to-HIGH and still be recognized. RECOVERY TIME (trec) -- is defined as the minimum time required between the end of the reset pulse and the clock transition from LOW-to-HIGH in order to recognize and transfer HIGH data to the Q outputs.
FAST AND LS TTL DATA 5-449
Case 751D-03 DW Suffix 20-Pin Plastic SO-20 (WIDE) -A20 11
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. 3. CONTROLLING DIMENSION: MILLIMETER. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE.
-B1 10
P
0.25 (0.010)
M
B
M
5.
751D 01, AND 02 OBSOLETE, NEW STANDARD 751D 03.
10 PL
G R X 45 -TC K
M
SEATING PLANE
M D 20 PL
0.25 (0.010) T B
S
F
J
DIM A B C D F G J K M P R
MILLIMETERS MIN MAX
12.65 7.40 2.35 0.35 0.50 12.95 7.60 2.65 0.49 0.90
INCHES MIN MAX
0.499 0.292 0.093 0.014 0.020 0.510 0.299 0.104 0.019 0.035
1.27 BSC 0.25 0.10 0 10.05 0.25 0.32 0.25 7 10.55 0.75
0.050 BSC 0.010 0.004 0 0.395 0.010 0.012 0.009 7 0.415 0.029
A
S
Case 732-03 J Suffix 20-Pin Ceramic Dual In-Line
NOTES: 1. LEADS WITHIN 0.25 mm (0.010) DIA., TRUE POSITION AT SEATING PLANE, AT MAXIMUM
20 1
11
2.
MATERIAL CONDITION. DIM L TO CENTER OF LEADS WHEN FORMED PARALLEL.
10
3.
DIM A AND B INCLUDES MENISCUS.
B A F C L
N H D
SEATING PLANE
J M
G
K
DIM A B C D F G H J K L M N
MILLIMETERS MIN MAX
23.88 6.60 3.81 0.38 1.40 25.15 7.49 5.08 0.56 1.65
INCHES MIN MAX
0.940 0.260 0.150 0.015 0.055 0.990 0.295 0.200 0.022 0.065
2.54 BSC 0.51 0.20 3.18 1.27 0.30 4.06
0.100 BSC 0.020 0.008 0.125 0.050 0.012 0.160
7.62 BSC 0 0.25 15 1.02
0.300 BSC 0 0.010 15 0.040
Case 738-03 N Suffix 20-Pin Plastic -A20 1 11 10
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. 3. CONTROLLING DIMENSION: INCH. DIMENSION L" TO CENTER OF LEAD WHEN FORMED PARALLEL.
B C L
4.
DIMENSION B" DOES NOT INCLUDE MOLD FLASH.
5.
738 02 OBSOLETE, NEW STANDARD 738 03.
-TSEATING PLANE
K E G F D 20 PL
0.25 (0.010)
M
N
M J 20 PL
0.25 (0.010) T A
M M
T
B
M
DIM A B C D E F G J K L M N
MILLIMETERS MIN MAX
25.66 6.10 3.81 0.39 27.17 6.60 4.57 0.55
INCHES MIN MAX
1.010 0.240 0.150 0.015 1.070 0.260 0.180 0.022
1.27 BSC 1.27 1.77
0.050 BSC 0.050 0.070
2.54 BSC 0.21 2.80 0.38 3.55
0.100 BSC 0.008 0.110 0.015 0.140
7.62 BSC 0 0.51 15 1.01
0.300 BSC 0 0.020 15 0.040
FAST AND LS TTL DATA 5-450
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters can and do vary in different applications. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer.
Literature Distribution Centers: USA: Motorola Literature Distribution; P.O. Box 20912; Phoenix, Arizona 85036. tPZH Open Closed EUROPE: Motorola Ltd.; European Literature Centre; 88 Tanners Drive, Blakelands, Milton Keynes, MK14 5BP, England. JAPAN: Nippon Motorola Ltd.; 4-32-1, Nishi-Gotanda, Shinagawa-ku, Tokyo 141, Japan. tPZL Closed Open ASIA PACIFIC: Motorola Semiconductors H.K. Ltd.; Silicon Harbour Center, No. 2 Dai King Street, Tai Po Industrial Estate, Tai Po, N.T., Hong Kong.
SYMBOL
SW1
SW2
tPLZ
Closed Closed
Closed Closed
tPHZ
FAST AND LS TTL DATA 5-451

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